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Author SHA1 Message Date
Michal Kubecek b71c1b9e0b import Workstation 15.0.1 module sources 2018-11-12 07:53:50 +01:00
5 changed files with 21 additions and 28 deletions

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+20 -6
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@@ -1092,8 +1092,9 @@ TaskSetCrossGDTVMM(BSVMM_GDTInit *gdt)
* TaskSetCrossGDTHost --
*
* Initializes the host portion of the crossGDT by copying it directly
* from the host kernel's GDT. We assume that all the host segments we
* will ever need come from the first page of the host's GDT.
* from the host kernel's GDT. We assume that all the host segments
* we will ever need come from the first page of the host's GDT and
* precede the lowest segment needed by the monitor.
*
* Results:
* TRUE on success, FALSE otherwise.
@@ -1105,17 +1106,30 @@ TaskSetCrossGDTVMM(BSVMM_GDTInit *gdt)
*/
static void
TaskSetCrossGDTHost(void)
TaskSetCrossGDTHost(const BSVMM_GDTInit *gdt)
{
unsigned len;
DTR64 hostGDT;
unsigned i;
/* Copy descriptors up to at most the size of the CrossGDT. */
unsigned minVMMIndex = sizeof(CrossGDT) / sizeof(Descriptor);
/*
* All copied host segment descriptors will come from the first page of
* the host kernel GDT.
* the host kernel GDT and precede the first monitor segment descriptor.
*/
ASSERT_ON_COMPILE(sizeof(CrossGDT) % sizeof(Descriptor) == 0);
ASSERT(HostIF_GlobalLockIsHeld());
for (i = 0; i < ARRAYSIZE(gdt->entries); i++) {
const BSVMM_GDTInitEntry *entry = &gdt->entries[i];
if (entry->present == 1) {
minVMMIndex = MIN(entry->index, minVMMIndex);
}
}
TaskSaveGDT(&hostGDT);
len = MIN((unsigned)hostGDT.limit + 1, sizeof(CrossGDT));
/* PR 2142795: Only copy up to at most the monitor's first descriptor. */
len = MIN((unsigned)hostGDT.limit + 1, minVMMIndex * sizeof(Descriptor));
ASSERT(len <= sizeof(CrossGDT));
memcpy(crossGDT->gdtes, (void*)HOST_KERNEL_LA_2_VA((LA)hostGDT.offset), len);
}
@@ -1157,7 +1171,7 @@ Task_CreateCrossGDT(BSVMM_GDTInit *gdt)
return FALSE;
}
memset(crossGDT, 0, sizeof *crossGDT);
TaskSetCrossGDTHost();
TaskSetCrossGDTHost(gdt);
}
populatedCrossGDT = TaskSetCrossGDTVMM(gdt);
+1 -2
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@@ -67,7 +67,6 @@ extern "C" {
#if defined (VMKPANIC)
#include "vmk_assert.h"
#else /* !VMKPANIC */
#include <linux/kernel.h>
#define _ASSERT_PANIC(name) \
Panic(_##name##Fmt "\n", __FILE__, __LINE__)
#define _ASSERT_PANIC_BUG(bug, name) \
@@ -108,7 +107,7 @@ NORETURN void Panic_NoSave(const char *fmt, ...) PRINTF_DECL(1, 2);
} while(0)
#else
#define Panic panic
NORETURN void Panic(const char *fmt, ...) PRINTF_DECL(1, 2);
#endif
void LogThrottled(uint32 *count, const char *fmt, ...) PRINTF_DECL(2, 3);
-4
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@@ -35,8 +35,6 @@
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include <asm/processor-flags.h>
#define X86_MAX_INSTR_LEN 15 /* Max byte length of an x86 instruction. */
#define NUM_IDT_VECTORS 256
@@ -77,9 +75,7 @@
#define CR3_PDB_MASK 0xfffff000
#define CR3_IGNORE 0xFFF
#define PAE_CR3_IGNORE 0x1F
#ifndef CR3_PCID_MASK
#define CR3_PCID_MASK 0xFFF
#endif
#define CR3_NO_FLUSH (1ULL << 63)
#define CR4_VME 0x00000001
-7
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@@ -24,7 +24,6 @@
#ifndef _X86MSR_H_
#define _X86MSR_H_
#include <asm/msr-index.h>
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMX
@@ -128,9 +127,7 @@ MSRQuery;
#define MSR_PRED_CMD_IBPB (1UL << 0)
#ifndef MSR_MISC_FEATURES_ENABLES
#define MSR_MISC_FEATURES_ENABLES 0x140
#endif
/* Intel Core Architecture and later: use only architected counters. */
#define IA32_MSR_PERF_CAPABILITIES 0x345
@@ -655,11 +652,7 @@ typedef unsigned char MTRRType;
/*
* MISC_FEATURES_ENABLES bits
*/
#ifdef MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULTING MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
#else
#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULTING 1
#endif
-9
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@@ -35,8 +35,6 @@
#endif
#endif
#include <linux/pci_ids.h>
/* LSILogic 53C1030 Parallel SCSI controller
* LSILogic SAS1068 SAS controller
*/
@@ -55,10 +53,7 @@
* VMware HD Audio codec
* VMware HD Audio controller
*/
#ifndef PCI_VENDOR_ID_VMWARE
#define PCI_VENDOR_ID_VMWARE 0x15AD
#endif
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
#define PCI_DEVICE_ID_VMWARE_VGA 0x0711
@@ -75,11 +70,7 @@
#define PCI_DEVICE_ID_VMWARE_1394 0x0780
#define PCI_DEVICE_ID_VMWARE_BRIDGE 0x0790
#define PCI_DEVICE_ID_VMWARE_ROOTPORT 0x07A0
#ifndef PCI_DEVICE_ID_VMWARE_VMXNET3
#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
#endif
#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
#define PCI_DEVICE_ID_VMWARE_82574 0x07D0
#define PCI_DEVICE_ID_VMWARE_AHCI 0x07E0