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Commits
| Author | SHA1 | Date | |
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74fd4e32eb | ||
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19f28078f1 | ||
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bbc8cdecd9 | ||
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50cc9223be |
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@@ -43,7 +43,6 @@ install: retiredcheck $(MODFILES)
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if test -z "$(DESTDIR)"; then $(DEPMOD) -a $(VM_UNAME); fi
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clean: $(SUBDIRS)
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rm -f *.o
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tarballs: $(TARBALLS)
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@@ -144,7 +144,7 @@ PtrToVA64(void const *ptr) // IN
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*
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*/
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#define VMMON_VERSION (331 << 16 | 0)
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#define VMMON_VERSION (330 << 16 | 0)
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#define VMMON_VERSION_MAJOR(v) ((uint32) (v) >> 16)
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#define VMMON_VERSION_MINOR(v) ((uint16) (v))
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@@ -35,6 +35,8 @@
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#define INCLUDE_ALLOW_VMCORE
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#include "includeCheck.h"
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#include <asm/processor-flags.h>
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#define X86_MAX_INSTR_LEN 15 /* Max byte length of an x86 instruction. */
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#define NUM_IDT_VECTORS 256
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@@ -75,7 +77,9 @@
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#define CR3_PDB_MASK 0xfffff000
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#define CR3_IGNORE 0xFFF
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#define PAE_CR3_IGNORE 0x1F
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#ifndef CR3_PCID_MASK
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#define CR3_PCID_MASK 0xFFF
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#endif
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#define CR3_NO_FLUSH (1ULL << 63)
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#define CR4_VME 0x00000001
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@@ -460,11 +460,8 @@ FLAG( 6, 0, ECX, 0, 1, HW_COORD_FEEDBACK, NO, 0, FALSE) \
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FLAG( 6, 0, ECX, 1, 1, ACNT2, ANY, 13, FALSE) \
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FLAG( 6, 0, ECX, 3, 1, ENERGY_PERF_BIAS, NO, 0, FALSE)
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#define CPUID_7_EDX_28 \
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FLAG( 7, 0, EDX, 28, 1, LEVEL7EDX_RSVD1, NO, 0, FALSE)
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#define CPUID_7_EDX_31 \
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FLAG( 7, 0, EDX, 31, 1, LEVEL7EDX_RSVD2, NO, 0, FALSE)
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FLAG( 7, 0, EDX, 31, 1, LEVEL7EDX_RSVD1, NO, 0, FALSE)
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/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV, CPL3 */
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#define CPUID_FIELD_DATA_LEVEL_7 \
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@@ -506,7 +503,6 @@ FLAG( 7, 0, ECX, 4, 1, OSPKE, ANY, 13, TRUE) \
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FLAG( 7, 0, ECX, 30, 1, SGX_LC, NO, 0, FALSE) \
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FLAG( 7, 0, EDX, 26, 1, IBRSIBPB, ANY, 9, FALSE) \
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FLAG( 7, 0, EDX, 27, 1, STIBP, YES, 9, FALSE) \
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CPUID_7_EDX_28 \
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FLAG( 7, 0, EDX, 29, 1, ARCH_CAPABILITIES, ANY, 9, FALSE) \
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CPUID_7_EDX_31
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@@ -24,6 +24,7 @@
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#ifndef _X86MSR_H_
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#define _X86MSR_H_
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#include <asm/msr-index.h>
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_VMX
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@@ -119,14 +120,13 @@ MSRQuery;
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#define MSR_ARCH_CAPABILITIES_IBRS_ALL (1ULL << 1)
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#define MSR_ARCH_CAPABILITIES_RSBA (1ULL << 2)
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#define MSR_FLUSH_CMD 0x10b
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#define MSR_FLUSH_CMD_FLUSH_L1D 1
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#define MSR_SPEC_CTRL_IBRS (1UL << 0)
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#define MSR_SPEC_CTRL_STIBP (1UL << 1)
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#define MSR_PRED_CMD_IBPB (1UL << 0)
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#ifndef MSR_MISC_FEATURES_ENABLES
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#define MSR_MISC_FEATURES_ENABLES 0x140
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#endif
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/* Intel Core Architecture and later: use only architected counters. */
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#define IA32_MSR_PERF_CAPABILITIES 0x345
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@@ -628,7 +628,11 @@ typedef enum {
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/*
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* MISC_FEATURES_ENABLES bits
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*/
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#ifdef MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
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#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULTING MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
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#else
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#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULTING 1
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#endif
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@@ -1,5 +1,5 @@
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/*********************************************************
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* Copyright (C) 1998-2014,2016,2018 VMware, Inc. All rights reserved.
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* Copyright (C) 1998-2014,2016 VMware, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@@ -39,7 +39,6 @@
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#include "vm_basic_types.h"
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#include "x86types.h"
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#include "vm_pagetable.h"
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#include "x86paging_common.h"
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#define LM_PTE_PFN_MASK CONST64U(0xffffffffff000)
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#define LM_PTE_2_PFN(_pte) (((_pte) & LM_PTE_PFN_MASK) >> PT_PTE_PFN_SHIFT)
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@@ -71,8 +70,6 @@
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#define LM_MAKE_L1E(_pfn, _avail, _flags) LM_MAKE_PTE(_pfn, _avail, _flags)
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/*
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* x86-64 architecture requires implementations supporting less than
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* full 64-bit VAs to ensure that all virtual addresses are in canonical
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@@ -35,6 +35,8 @@
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#endif
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#endif
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#include <linux/pci_ids.h>
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/* LSILogic 53C1030 Parallel SCSI controller
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* LSILogic SAS1068 SAS controller
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*/
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@@ -53,7 +55,10 @@
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* VMware HD Audio codec
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* VMware HD Audio controller
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*/
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#ifndef PCI_VENDOR_ID_VMWARE
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#define PCI_VENDOR_ID_VMWARE 0x15AD
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#endif
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#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
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#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
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#define PCI_DEVICE_ID_VMWARE_VGA 0x0711
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@@ -70,7 +75,11 @@
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#define PCI_DEVICE_ID_VMWARE_1394 0x0780
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#define PCI_DEVICE_ID_VMWARE_BRIDGE 0x0790
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#define PCI_DEVICE_ID_VMWARE_ROOTPORT 0x07A0
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#ifndef PCI_DEVICE_ID_VMWARE_VMXNET3
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#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
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#endif
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#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
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#define PCI_DEVICE_ID_VMWARE_82574 0x07D0
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#define PCI_DEVICE_ID_VMWARE_AHCI 0x07E0
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