688 lines
19 KiB
C
688 lines
19 KiB
C
/*********************************************************
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* Copyright (C) 2013-2020 VMware, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation version 2 and no later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*********************************************************/
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/*
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* vm_basic_asm_x86_common.h --
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*
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* Basic assembler macros common to 32-bit and 64-bit x86 ISA.
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*/
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#ifndef _VM_BASIC_ASM_X86_COMMON_H_
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#define _VM_BASIC_ASM_X86_COMMON_H_
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_MODULE
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#define INCLUDE_ALLOW_VMMON
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#define INCLUDE_ALLOW_VMK_MODULE
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#define INCLUDE_ALLOW_VMKERNEL
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#define INCLUDE_ALLOW_DISTRIBUTE
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#define INCLUDE_ALLOW_VMCORE
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#include "includeCheck.h"
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#ifndef VM_X86_ANY
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#error "Should be included only in x86 builds"
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#endif
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#ifdef __GNUC__
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/*
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* Checked against the Intel manual and GCC --hpreg
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*
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* volatile because reading from port can modify the state of the underlying
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* hardware.
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*
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* Note: The undocumented %z construct doesn't work (internal compiler error)
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* with gcc-2.95.1
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*/
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#define __GCC_IN(s, type, name) \
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static INLINE type \
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name(uint16 port) \
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{ \
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type val; \
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\
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__asm__ __volatile__( \
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"in" #s " %w1, %0" \
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: "=a" (val) \
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: "Nd" (port) \
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); \
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\
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return val; \
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}
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__GCC_IN(b, uint8, INB)
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__GCC_IN(w, uint16, INW)
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__GCC_IN(l, uint32, IN32)
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/*
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* Checked against the Intel manual and GCC --hpreg
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*
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* Note: The undocumented %z construct doesn't work (internal compiler error)
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* with gcc-2.95.1
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*/
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#define __GCC_OUT(s, s2, port, val) do { \
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__asm__( \
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"out" #s " %" #s2 "1, %w0" \
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: \
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: "Nd" (port), "a" (val) \
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); \
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} while (0)
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#define OUTB(port, val) __GCC_OUT(b, b, port, val)
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#define OUTW(port, val) __GCC_OUT(w, w, port, val)
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#define OUT32(port, val) __GCC_OUT(l, , port, val)
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static INLINE unsigned int
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GetCallerEFlags(void)
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{
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unsigned long flags;
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asm volatile("pushf; pop %0" : "=r"(flags));
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return flags;
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}
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#elif defined(_MSC_VER)
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static INLINE uint8
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INB(uint16 port)
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{
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return __inbyte(port);
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}
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static INLINE void
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OUTB(uint16 port, uint8 value)
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{
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__outbyte(port, value);
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}
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static INLINE uint16
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INW(uint16 port)
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{
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return __inword(port);
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}
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static INLINE void
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OUTW(uint16 port, uint16 value)
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{
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__outword(port, value);
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}
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static INLINE uint32
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IN32(uint16 port)
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{
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return __indword(port);
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}
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static INLINE void
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OUT32(uint16 port, uint32 value)
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{
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__outdword(port, value);
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}
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#ifndef VM_X86_64
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#ifdef NEAR
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#undef NEAR
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#endif
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#endif // VM_X86_64
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static INLINE unsigned int
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GetCallerEFlags(void)
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{
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return __getcallerseflags();
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}
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#endif // __GNUC__
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/* Sequence recommended by Intel for the Pentium 4. */
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#define INTEL_MICROCODE_VERSION() ( \
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X86MSR_SetMSR(MSR_BIOS_SIGN_ID, 0), \
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__GET_EAX_FROM_CPUID(1), \
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X86MSR_GetMSR(MSR_BIOS_SIGN_ID))
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/*
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*-----------------------------------------------------------------------------
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*
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* MFENCE --
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*
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* Wrapper around the MFENCE instruction.
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*
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* Caveat Emptor! This function is _NOT_ _PORTABLE_ and most certainly
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* not something you should use. Take a look at the SMP_*_BARRIER_*,
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* DMA_*_BARRIER_* and MMIO_*_BARRIER_* interfaces instead, when writing
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* general OS/VMM code.
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*
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* Results:
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* None.
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*
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* Side effects:
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* See MFENCE instruction in Intel SDM or AMD Programmer's Manual.
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*
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*-----------------------------------------------------------------------------
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*/
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static INLINE void
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MFENCE(void)
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{
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#ifdef __GNUC__
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__asm__ __volatile__(
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"mfence"
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::: "memory"
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);
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#elif defined _MSC_VER
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_ReadWriteBarrier();
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_mm_mfence();
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_ReadWriteBarrier();
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#else
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#error No compiler defined for MFENCE
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#endif
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}
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/*
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*-----------------------------------------------------------------------------
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*
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* LFENCE --
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*
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* Wrapper around the LFENCE instruction.
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*
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* Caveat Emptor! This function is _NOT_ _PORTABLE_ and most certainly
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* not something you should use. Take a look at the SMP_*_BARRIER_*,
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* DMA_*_BARRIER_* and MMIO_*_BARRIER_* interfaces instead, when writing
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* general OS/VMM code.
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*
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* Results:
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* None.
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*
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* Side effects:
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* See LFENCE instruction in Intel SDM or AMD Programmer's Manual.
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*
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*-----------------------------------------------------------------------------
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*/
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static INLINE void
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LFENCE(void)
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{
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#ifdef __GNUC__
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__asm__ __volatile__(
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"lfence"
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: : : "memory"
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);
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#elif defined _MSC_VER
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_ReadWriteBarrier();
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_mm_lfence();
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_ReadWriteBarrier();
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#else
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#error No compiler defined for LFENCE
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#endif
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}
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/*
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*-----------------------------------------------------------------------------
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*
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* SFENCE --
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*
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* Wrapper around the SFENCE instruction.
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*
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* Caveat Emptor! This function is _NOT_ _PORTABLE_ and most certainly
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* not something you should use. Take a look at the SMP_*_BARRIER_*,
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* DMA_*_BARRIER_* and MMIO_*_BARRIER_* interfaces instead, when writing
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* general OS/VMM code.
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*
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* Results:
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* None.
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*
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* Side effects:
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* See SFENCE instruction in Intel SDM or AMD Programmer's Manual.
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*
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*-----------------------------------------------------------------------------
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*/
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static INLINE void
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SFENCE(void)
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{
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#ifdef __GNUC__
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__asm__ __volatile__(
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"sfence"
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: : : "memory"
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);
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#elif defined _MSC_VER
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_ReadWriteBarrier();
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_mm_sfence();
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_ReadWriteBarrier();
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#else
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#error No compiler defined for SFENCE
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#endif
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}
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/*
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*-----------------------------------------------------------------------------
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*
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* RDTSC_BARRIER --
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*
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* Implements an RDTSC fence. Instructions executed prior to the
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* fence will have completed before the fence and all stores to
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* memory are flushed from the store buffer.
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*
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* On AMD, MFENCE is sufficient. On Intel, only LFENCE is
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* documented to fence RDTSC, but LFENCE won't drain the store
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* buffer. So, use MFENCE;LFENCE, which will work on both AMD and
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* Intel.
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*
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* It is the callers' responsibility to check for SSE2 before
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* calling this function.
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*
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* Results:
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* None.
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*
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* Side effects:
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* Cause loads and stores prior to this to be globally visible, and
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* RDTSC will not pass.
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*
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*-----------------------------------------------------------------------------
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*/
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static INLINE void
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RDTSC_BARRIER(void)
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{
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MFENCE();
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LFENCE();
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}
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/*
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*-----------------------------------------------------------------------------
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*
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* LOCKED_INSN_BARRIER --
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*
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* Implements a full WB load/store barrier using a locked instruction.
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*
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* See PR 1674199 for details. You may choose to use this for
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* performance reasons over MFENCE iff you are only dealing with
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* WB memory accesses.
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*
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* DANGER! Do not use this barrier instead of MFENCE when dealing
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* with non-temporal instructions or UC/WC memory accesses.
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*
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* Caveat Emptor! This function is _NOT_ _PORTABLE_ and most certainly
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* not something you should use. Take a look at the SMP_*_BARRIER_*,
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* DMA_*_BARRIER_* and MMIO_*_BARRIER_* interfaces instead, when writing
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* general OS/VMM code.
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*
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* Results:
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* None.
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*
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* Side effects:
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* Cause WB loads and stores before the call to be globally visible
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* before WB loads and stores after this call.
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*
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*-----------------------------------------------------------------------------
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*/
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static INLINE void
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LOCKED_INSN_BARRIER(void)
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{
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volatile long temp = 0;
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#if defined __GNUC__
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__asm__ __volatile__ (
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"lock xorl $1, %0"
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: "+m" (temp)
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: /* no additional inputs */
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: "cc", "memory");
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#elif defined _MSC_VER
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/*
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* Ignore warning about _InterlockedXor operation on a local variable; we are
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* using the operation for its side-effects only.
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*/
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#pragma warning(suppress:28113)
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_InterlockedXor(&temp, 1);
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#else
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#error LOCKED_INSN_BARRIER not defined for this compiler
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#endif
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}
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/*
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* Memory Barriers
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* ===============
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*
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* Terminology
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* -----------
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*
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* A compiler memory barrier prevents the compiler from re-ordering memory
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* accesses accross the barrier. It is not a CPU instruction, it is a compiler
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* directive (i.e. it does not emit any code).
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*
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* A CPU memory barrier prevents the CPU from re-ordering memory accesses
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* accross the barrier. It is a CPU instruction.
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*
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* A memory barrier is the union of a compiler memory barrier and a CPU memory
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* barrier. A compiler memory barrier is a useless construct by itself. It is
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* only useful when combined with a CPU memory barrier, to implement a memory
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* barrier.
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*
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* Semantics
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* ---------
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*
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* At the time COMPILER_*_BARRIER were created (and references to them were
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* added to the code), the code was only targetting x86. The intent of the code
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* was really to use a memory barrier, but because x86 uses a strongly ordered
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* memory model, the CPU would not re-order memory accesses, and the code could
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* get away with using just a compiler memory barrier. So COMPILER_*_BARRIER
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* were born and were implemented as compiler memory barriers _on x86_. But
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* make no mistake, _the semantics that the code expects from
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* COMPILER_*_BARRIER are that of a memory barrier_!
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*
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* DO NOT USE!
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* -----------
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*
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* On at least one non-x86 architecture, COMPILER_*_BARRIER are
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* 1) Misnomers
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* 2) Not fine-grained enough to provide the best performance.
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* For the above two reasons, usage of COMPILER_*_BARRIER is now deprecated.
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* _Do not add new references to COMPILER_*_BARRIER._ Instead, precisely
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* document the intent of your code by using
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* <mem_type/purpose>_<before_access_type>_BARRIER_<after_access_type>.
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* Existing references to COMPILER_*_BARRIER are being slowly but surely
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* converted, and when no references are left, COMPILER_*_BARRIER will be
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* retired.
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*
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* Thanks for pasting this whole comment into every architecture header.
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*/
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#if defined __GNUC__
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# define COMPILER_READ_BARRIER() COMPILER_MEM_BARRIER()
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# define COMPILER_WRITE_BARRIER() COMPILER_MEM_BARRIER()
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# define COMPILER_MEM_BARRIER() __asm__ __volatile__("" ::: "memory")
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#elif defined _MSC_VER
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# define COMPILER_READ_BARRIER() _ReadBarrier()
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# define COMPILER_WRITE_BARRIER() _WriteBarrier()
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# define COMPILER_MEM_BARRIER() _ReadWriteBarrier()
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#endif
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/*
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* Memory barriers. These take the form of
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*
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* <mem_type/purpose>_<before_access_type>_BARRIER_<after_access_type>
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*
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* where:
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* <mem_type/purpose> is either SMP, DMA, or MMIO.
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* <*_access type> is either R(load), W(store) or RW(any).
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*
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* Above every use of these memory barriers in the code, there _must_ be a
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* comment to justify the use, i.e. a comment which:
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*
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* 1) Precisely identifies which memory accesses must not be re-ordered across
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* the memory barrier.
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* 2) Explains why it is important that the memory accesses not be re-ordered.
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*
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* Thanks for pasting this whole comment into every architecture header.
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*
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* This is a simplified version of Table 7-3 (Memory Access Ordering Rules) from
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* AMD AMD64 Architecture Programmer's Manual Volume 2: System Programming
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* (September 2018, Publication 24593, Revision 3.30).
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*
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* https://www.amd.com/system/files/TechDocs/24593.pdf#page=228
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*
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* This table only includes the memory types we care about in the context of
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* SMP, DMA and MMIO barriers.
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*
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* +-------------+------+------+------+------+------+------+
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* |\ 2nd mem op | | | | | | |
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* | `---------. | R WB | R UC | R WC | W WB | W UC | W WC |
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* | 1st mem op \| | | | | | |
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* +-------------+------+------+------+------+------+------+
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* | R WB | | | LF1 | | | |
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* +-------------+------+------+------+------+------+------+
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* | R UC | | | LF1 | | | |
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* +-------------+------+------+------+------+------+------+
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* | R WC | | | LF1 | | | |
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* +-------------+------+------+------+------+------+------+
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* | W WB | MF1 | | MF1 | | | SF2 |
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* +-------------+------+------+------+------+------+------+
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* | W UC | MF1 | | MF1 | | | SF2 |
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* +-------------+------+------+------+------+------+------+
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* | W WC | MF1 | | MF1 | SF1 | | SF2 |
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* +-------------+------+------+------+------+------+------+
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*
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* MF1 - WB or WC load may pass a previous non-conflicting WB, WC or UC store.
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* Use MFENCE. This is a combination of rules 'e' and 'i' in the AMD
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* diagram.
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* LF1 - WC load may pass a previous WB, WC or UC load. Use LFENCE. This is
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* rule 'b' in the AMD diagram.
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* SF1 - WB store may pass a previous WC store. Use SFENCE. This is rule 'j' in
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* the AMD diagram.
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* SF2 - WC store may pass a previous UC, WB or non-conflicting WC store. Use
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* SFENCE. This is rule 'h' in the AMD diagram.
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*
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* To figure out the specific barrier required, pick and collapse the relevant
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* rows and columns, choosing the strongest barrier.
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*
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* SMP barriers only concern with access to "normal memory" (write-back cached
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* i.e. WB using above terminology), so we only need to worry about store-load
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* reordering. In other cases a compiler barrier is sufficient. SMP store-load
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* reordering is handled with a locked XOR (instead of a proper MFENCE
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* instructon) for performance reasons. See PR 1674199 for more details.
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*
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* DMA barriers are equivalent to SMP barriers on x86.
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*
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* MMIO barriers are used to mix access to different memory types, so more
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* reordering is possible, and is handled via LFENCE/SFENCE. Also, a proper
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* MFENCE must be used instead of the locked XOR trick, due to the latter
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* not guarding non-temporal/WC accesses.
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*/
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#define SMP_R_BARRIER_R() COMPILER_READ_BARRIER()
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#define SMP_R_BARRIER_W() COMPILER_MEM_BARRIER()
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#define SMP_R_BARRIER_RW() COMPILER_MEM_BARRIER()
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#define SMP_W_BARRIER_R() LOCKED_INSN_BARRIER()
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#define SMP_W_BARRIER_W() COMPILER_WRITE_BARRIER()
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#define SMP_W_BARRIER_RW() LOCKED_INSN_BARRIER()
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#define SMP_RW_BARRIER_R() LOCKED_INSN_BARRIER()
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#define SMP_RW_BARRIER_W() COMPILER_MEM_BARRIER()
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#define SMP_RW_BARRIER_RW() LOCKED_INSN_BARRIER()
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/*
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* Like the above, only for use with observers other than CPUs,
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* i.e. DMA masters. Same as SMP barriers for x86.
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*/
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#define DMA_R_BARRIER_R() SMP_R_BARRIER_R()
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#define DMA_R_BARRIER_W() SMP_R_BARRIER_W()
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#define DMA_R_BARRIER_RW() SMP_R_BARRIER_RW()
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#define DMA_W_BARRIER_R() SMP_W_BARRIER_R()
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#define DMA_W_BARRIER_W() SMP_W_BARRIER_W()
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#define DMA_W_BARRIER_RW() SMP_W_BARRIER_RW()
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#define DMA_RW_BARRIER_R() SMP_RW_BARRIER_R()
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#define DMA_RW_BARRIER_W() SMP_RW_BARRIER_W()
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#define DMA_RW_BARRIER_RW() SMP_RW_BARRIER_RW()
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/*
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* And finally a set for use with MMIO accesses. These barriers must be stronger
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* because they are used when mixing accesses to different memory types.
|
|
*/
|
|
|
|
#define MMIO_R_BARRIER_R() LFENCE()
|
|
#define MMIO_R_BARRIER_W() SMP_R_BARRIER_W()
|
|
#define MMIO_R_BARRIER_RW() LFENCE()
|
|
#define MMIO_W_BARRIER_R() MFENCE()
|
|
#define MMIO_W_BARRIER_W() SFENCE()
|
|
#define MMIO_W_BARRIER_RW() MFENCE()
|
|
#define MMIO_RW_BARRIER_R() MFENCE()
|
|
#define MMIO_RW_BARRIER_W() SFENCE()
|
|
#define MMIO_RW_BARRIER_RW() MFENCE()
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIORead8 --
|
|
*
|
|
* IO read from address "addr".
|
|
*
|
|
* Results:
|
|
* 8-bit value at given location.
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE uint8
|
|
MMIORead8(const volatile void *addr)
|
|
{
|
|
volatile uint8 *addr8 = (volatile uint8 *) addr;
|
|
|
|
return *addr8;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIOWrite8 --
|
|
*
|
|
* IO write to address "addr".
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE void
|
|
MMIOWrite8(volatile void *addr, // IN
|
|
uint8 val) // IN
|
|
{
|
|
volatile uint8 *addr8 = (volatile uint8 *) addr;
|
|
|
|
*addr8 = val;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIORead16 --
|
|
*
|
|
* IO read from address "addr".
|
|
*
|
|
* Results:
|
|
* 16-bit value at given location.
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE uint16
|
|
MMIORead16(const volatile void *addr)
|
|
{
|
|
volatile uint16 *addr16 = (volatile uint16 *) addr;
|
|
|
|
return *addr16;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIOWrite16 --
|
|
*
|
|
* IO write to address "addr".
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE void
|
|
MMIOWrite16(volatile void *addr, // IN
|
|
uint16 val) // IN
|
|
{
|
|
volatile uint16 *addr16 = (volatile uint16 *) addr;
|
|
|
|
*addr16 = val;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIORead32 --
|
|
*
|
|
* IO read from address "addr".
|
|
*
|
|
* Results:
|
|
* 32-bit value at given location.
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE uint32
|
|
MMIORead32(const volatile void *addr)
|
|
{
|
|
volatile uint32 *addr32 = (volatile uint32 *) addr;
|
|
|
|
return *addr32;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIOWrite32 --
|
|
*
|
|
* IO write to address "addr".
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE void
|
|
MMIOWrite32(volatile void *addr, // OUT
|
|
uint32 val)
|
|
{
|
|
volatile uint32 *addr32 = (volatile uint32 *) addr;
|
|
|
|
*addr32 = val;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIORead64 --
|
|
*
|
|
* IO read from address "addr".
|
|
*
|
|
* Results:
|
|
* 64-bit value at given location.
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE uint64
|
|
MMIORead64(const volatile void *addr)
|
|
{
|
|
volatile uint64 *addr64 = (volatile uint64 *) addr;
|
|
|
|
return *addr64;
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------------
|
|
*
|
|
* MMIOWrite64 --
|
|
*
|
|
* IO write to address "addr".
|
|
*
|
|
*----------------------------------------------------------------------
|
|
*/
|
|
static INLINE void
|
|
MMIOWrite64(volatile void *addr, // OUT
|
|
uint64 val)
|
|
{
|
|
volatile uint64 *addr64 = (volatile uint64 *) addr;
|
|
|
|
*addr64 = val;
|
|
}
|
|
|
|
#endif // _VM_BASIC_ASM_X86_COMMON_H_
|