264 lines
8.9 KiB
C
264 lines
8.9 KiB
C
/*********************************************************
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* Copyright (C) 2006-2016 VMware, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation version 2 and no later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*********************************************************/
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/*
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* x86_basic_defs.h --
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*
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* Basic macros describing the x86 architecture.
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*/
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#ifndef _X86_BASIC_DEFS_H_
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#define _X86_BASIC_DEFS_H_
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_MODULE
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#define INCLUDE_ALLOW_VMMON
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#define INCLUDE_ALLOW_VMK_MODULE
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#define INCLUDE_ALLOW_VMKERNEL
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#define INCLUDE_ALLOW_DISTRIBUTE
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#define INCLUDE_ALLOW_VMCORE
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#include "includeCheck.h"
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#define X86_MAX_INSTR_LEN 15 /* Max byte length of an x86 instruction. */
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#define NUM_IDT_VECTORS 256
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/*
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* control registers
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*/
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#define CR0_PE 0x00000001
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#define CR0_MP 0x00000002
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#define CR0_EM 0x00000004
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#define CR0_TS 0x00000008
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#define CR0_ET 0x00000010
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#define CR0_NE 0x00000020
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#define CR0_WP 0x00010000
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#define CR0_AM 0x00040000
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#define CR0_NW 0x20000000
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#define CR0_CD 0x40000000
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#define CR0_PG 0x80000000
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#define CR0_CACHE_CONTROL (CR0_CD | CR0_NW)
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#define CR0_RESERVED CONST64U(0xffffffff1ffaffc0)
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/*
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* Note: The "Not Reserved" bits in CR0 are:
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* PG, CD, NW, AM, WP, NE, ET, TS, EM, MP, PE
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* | | | | | |
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* | | +---------------+---+---+---> CR0_MUTABLE
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* | |
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* +---+--> CR0_CACHE_CONTROL
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*
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* (CR0_MUTABLE is defined in vmkernel/private/x86/cpu.h)
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*/
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#define CR3_PWT 0x00000008
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#define CR3_PCD 0x00000010
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#define CR3_PDB_SHIFT 12
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#define CR3_PDB_MASK 0xfffff000
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#define CR3_IGNORE 0xFFF
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#define PAE_CR3_IGNORE 0x1F
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#define CR3_PCID_MASK 0xFFF
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#define CR3_NO_FLUSH (1ULL << 63)
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#define CR4_VME 0x00000001
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#define CR4_PVI 0x00000002
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#define CR4_TSD 0x00000004
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#define CR4_DE 0x00000008
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#define CR4_PSE 0x00000010
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#define CR4_PAE 0x00000020
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#define CR4_MCE 0x00000040
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#define CR4_PGE 0x00000080
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#define CR4_PCE 0x00000100
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#define CR4_OSFXSR 0x00000200 // CPU/OS supports SIMD insts
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#define CR4_OSXMMEXCPT 0x00000400 // #XF exception enable PIII only
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#define CR4_VMXE 0x00002000
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#define CR4_SMXE 0x00004000
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#define CR4_FSGSBASE 0x00010000
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#define CR4_PCIDE 0x00020000
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#define CR4_OSXSAVE 0x00040000
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#define CR4_SMEP 0x00100000
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#define CR4_SMAP 0x00200000
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#define CR4_PKE 0x00400000
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#define CR4_RESERVED CONST64U(0xffffffffff889800)
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#define CR8_RESERVED CONST64U(0xfffffffffffffff0)
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/*
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* Debug registers.
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*/
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#define DR_COUNT 4
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#define DR6_B0 0x00000001
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#define DR6_B1 0x00000002
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#define DR6_B2 0x00000004
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#define DR6_B3 0x00000008
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#define DR6_B0123 (DR6_B0 | DR6_B1 | DR6_B2 | DR6_B3)
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#define DR6_B(_n) (1 << (_n))
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#define DR6_BD 0x00002000
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#define DR6_BS 0x00004000
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#define DR6_BT 0x00008000
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#define DR6_RTM 0x00010000
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#define DR6_ONES 0xfffe0ff0
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#define DR6_DEFAULT (DR6_ONES | DR6_RTM)
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#define DR6_RESERVED_MASK 0xfffe1ff0
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#define DR7_L_MASK(_n) (1 << ((_n) * 2))
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#define DR7_G_MASK(_n) (1 << ((_n) * 2 + 1))
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#define DR7_LG_MASK(_n) (3 << ((_n) * 2))
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#define DR7_RW_MASK(_n) (3 << (16 + (_n) * 4))
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#define DR7_LEN_MASK(_n) (3 << (18 + (_n) * 4))
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#define DR7_BP_MASK(_n) (DR7_L_MASK(_n) |\
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DR7_G_MASK(_n) |\
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DR7_RW_MASK(_n) |\
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DR7_LEN_MASK(_n))
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#define DR7_L0 DR7_L_MASK(0)
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#define DR7_G0 DR7_G_MASK(0)
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#define DR7_L1 DR7_L_MASK(1)
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#define DR7_G1 DR7_G_MASK(1)
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#define DR7_L2 DR7_L_MASK(2)
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#define DR7_G2 DR7_G_MASK(2)
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#define DR7_L3 DR7_L_MASK(3)
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#define DR7_G3 DR7_G_MASK(3)
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#define DR7_ENABLED 0x000000ff
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#define DR7_LE 0x00000100 // Deprecated in modern hardware
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#define DR7_GE 0x00000200 // Deprecated in modern hardware
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#define DR7_GD 0x00002000
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#define DR7_ONES 0x00000400
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#define DR7_RTM 0x00000800
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#define DR7_RESERVED CONST64U(0xffffffff0000d400)
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#define DR7_DEFUNCT (DR7_LE | DR7_GE)
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#define DR7_DEFAULT DR7_ONES
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#define DR7_LX_MASK (DR7_L0 | DR7_L1 | DR7_L2 | DR7_L3 | DR7_LE)
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#define DR7_GX_MASK (DR7_G0 | DR7_G1 | DR7_G2 | DR7_G3 | DR7_GE)
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#define DR7_LGX_MASK (DR7_LX_MASK | DR7_GX_MASK)
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#define DR7_RW(_r,_n) (((_r) >> (16+(_n)*4)) & 0x3)
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#define DR7_L(_r,_n) (((_r) >> ((_n)*2)) & 1)
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#define DR7_G(_r,_n) (((_r) >> (1 + (_n)*2)) & 1)
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#define DR7_LEN(_r,_n) (((_r) >> (18+(_n)*4)) & 0x3)
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#define DR7_RW_BITS(_n,_rw) ((_rw) << (16 + (_n) * 4))
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#define DR7_LEN_BITS(_n,_len) ((_len) << (18 + (_n) * 4))
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#define DR7_RW_INST 0x0
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#define DR7_RW_WRITES 0x1
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#define DR7_RW_IO 0x2
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#define DR7_RW_ACCESS 0x3
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#define DR7_LENGTH_1 0x0
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#define DR7_LENGTH_2 0x1
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#define DR7_LENGTH_8 0x2
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#define DR7_LENGTH_4 0x3
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#define DEBUG_STATUS_B0 (1<<0)
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#define DEBUG_STATUS_B1 (1<<1)
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#define DEBUG_STATUS_B2 (1<<2)
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#define DEBUG_STATUS_B3 (1<<3)
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#define DEBUG_STATUS_DB (1<<13)
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#define DEBUG_STATUS_BS (1<<14)
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#define DEBUG_STATUS_BT (1<<15)
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/*
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* exception error codes
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*/
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#define EXC_DE 0
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#define EXC_DB 1
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#define EXC_NMI 2
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#define EXC_BP 3
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#define EXC_OF 4
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#define EXC_BR 5
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#define EXC_UD 6
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#define EXC_NM 7
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#define EXC_DF 8
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#define EXC_TS 10
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#define EXC_NP 11
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#define EXC_SS 12
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#define EXC_GP 13
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#define EXC_PF 14
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#define EXC_MF 16
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#define EXC_AC 17
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#define EXC_MC 18
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#define EXC_XF 19 // SIMD exception.
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#define EXC_VE 20 // Virtualization exception - VT only.
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#define EXC_SX 30 // Security exception (SVM only).
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/*
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* eflag/rflag definitions.
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*/
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#define EFLAGS_IOPL_SHIFT 12
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typedef enum x86_FLAGS {
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EFLAGS_NONE = 0,
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EFLAGS_CF = (1 << 0), /* User */
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EFLAGS_SET = (1 << 1),
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EFLAGS_PF = (1 << 2), /* User */
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EFLAGS_AF = (1 << 4), /* User */
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EFLAGS_ZF = (1 << 6), /* User */
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EFLAGS_SF = (1 << 7), /* User */
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EFLAGS_TF = (1 << 8), /* Priv */
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EFLAGS_IF = (1 << 9), /* Priv */
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EFLAGS_DF = (1 << 10), /* User */
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EFLAGS_OF = (1 << 11), /* User */
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EFLAGS_NT = (1 << 14), /* Priv */
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EFLAGS_RF = (1 << 16), /* Priv */
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EFLAGS_VM = (1 << 17), /* Priv */
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EFLAGS_AC = (1 << 18), /* Priv */
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EFLAGS_VIF = (1 << 19), /* Priv */
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EFLAGS_VIP = (1 << 20), /* Priv */
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EFLAGS_ID = (1 << 21), /* Priv */
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EFLAGS_IOPL = 3 << EFLAGS_IOPL_SHIFT,
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EFLAGS_ARITH = (EFLAGS_CF | EFLAGS_PF | EFLAGS_AF | EFLAGS_ZF |
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EFLAGS_SF | EFLAGS_OF),
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EFLAGS_USER = (EFLAGS_CF | EFLAGS_PF | EFLAGS_AF | EFLAGS_ZF |
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EFLAGS_SF | EFLAGS_DF | EFLAGS_OF),
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EFLAGS_PRIV = (EFLAGS_TF | EFLAGS_IF | EFLAGS_IOPL | EFLAGS_NT |
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EFLAGS_RF | EFLAGS_VM | EFLAGS_AC | EFLAGS_VIF |
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EFLAGS_VIP | EFLAGS_ID),
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EFLAGS_ALL = (EFLAGS_CF | EFLAGS_PF | EFLAGS_AF | EFLAGS_ZF |
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EFLAGS_SF | EFLAGS_DF | EFLAGS_OF | EFLAGS_TF |
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EFLAGS_IF | EFLAGS_IOPL | EFLAGS_NT | EFLAGS_RF |
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EFLAGS_VM | EFLAGS_AC | EFLAGS_VIF | EFLAGS_VIP |
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EFLAGS_ID),
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EFLAGS_ALL_16 = EFLAGS_ALL & 0xffff,
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EFLAGS_REAL_32 = (EFLAGS_ALL & ~(EFLAGS_VIP | EFLAGS_VIF | EFLAGS_VM)),
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EFLAGS_V8086_32 = (EFLAGS_ALL & ~(EFLAGS_VIP | EFLAGS_VIF |
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EFLAGS_VM | EFLAGS_IOPL)),
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EFLAGS_REAL_16 = EFLAGS_REAL_32 & 0xffff,
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EFLAGS_V8086_16 = EFLAGS_V8086_32 & 0xffff,
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EFLAGS_CLEAR_ON_EXC = (EFLAGS_TF | EFLAGS_VM | EFLAGS_RF | EFLAGS_NT),
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EFLAGS__4 = 0x7fffffff /* ensure 4 byte encoding */
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} x86_FLAGS;
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/*
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* MPX bound configuration registers
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*/
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#define BNDCFG_EN 0x00000001
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#define BNDCFG_BNDPRSV 0x00000002
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#define BNDCFG_RSVD 0x00000ffc
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#define BNDCFG_BDBASE CONST64U(0xfffffffffffff000)
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#endif // ifndef _VM_BASIC_DEFS_H_
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