447 lines
14 KiB
C
447 lines
14 KiB
C
/*********************************************************
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* Copyright (C) 2013-2017 VMware, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation version 2 and no later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*********************************************************/
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/*
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* vm_basic_asm_x86_common.h --
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*
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* Basic assembler macros common to 32-bit and 64-bit x86 ISA.
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*/
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#ifndef _VM_BASIC_ASM_X86_COMMON_H_
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#define _VM_BASIC_ASM_X86_COMMON_H_
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_MODULE
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#define INCLUDE_ALLOW_VMMON
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#define INCLUDE_ALLOW_VMK_MODULE
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#define INCLUDE_ALLOW_VMKERNEL
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#define INCLUDE_ALLOW_DISTRIBUTE
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#define INCLUDE_ALLOW_VMCORE
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#include "includeCheck.h"
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#ifndef VM_X86_ANY
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#error "Should be included only in x86 builds"
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#endif
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/*
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* x86-64 windows doesn't support inline asm so we have to use these
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* intrinsic functions defined in the compiler. Not all of these are well
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* documented. There is an array in the compiler dll (c1.dll) which has
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* an array of the names of all the intrinsics minus the leading
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* underscore. Searching around in the ntddk.h file can also be helpful.
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*
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* The declarations for the intrinsic functions were taken from the DDK.
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* Our declarations must match the ddk's otherwise the 64-bit c++ compiler
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* will complain about second linkage of the intrinsic functions.
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* We define the intrinsic using the basic types corresponding to the
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* Windows typedefs. This avoids having to include windows header files
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* to get to the windows types.
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*/
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#if defined(_MSC_VER) && !defined(BORA_NO_WIN32_INTRINS)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* It seems x86 & x86-64 windows still implements these intrinsic
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* functions. The documentation for the x86-64 suggest the
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* __inbyte/__outbyte intrinsics even though the _in/_out work fine and
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* __inbyte/__outbyte aren't supported on x86.
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*/
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int _inp(unsigned short);
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unsigned short _inpw(unsigned short);
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unsigned long _inpd(unsigned short);
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int _outp(unsigned short, int);
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unsigned short _outpw(unsigned short, unsigned short);
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unsigned long _outpd(uint16, unsigned long);
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#pragma intrinsic(_inp, _inpw, _inpd, _outp, _outpw, _outpw, _outpd)
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/*
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* Prevents compiler from re-ordering reads, writes and reads&writes.
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* These functions do not add any instructions thus only affect
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* the compiler ordering.
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*
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* See:
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* `Lockless Programming Considerations for Xbox 360 and Microsoft Windows'
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* http://msdn.microsoft.com/en-us/library/bb310595(VS.85).aspx
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*/
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void _ReadBarrier(void);
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void _WriteBarrier(void);
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void _ReadWriteBarrier(void);
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#pragma intrinsic(_ReadBarrier, _WriteBarrier, _ReadWriteBarrier)
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void _mm_mfence(void);
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void _mm_lfence(void);
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#pragma intrinsic(_mm_mfence, _mm_lfence)
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long _InterlockedXor(long volatile *, long);
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#pragma intrinsic(_InterlockedXor)
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unsigned int __getcallerseflags(void);
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#pragma intrinsic(__getcallerseflags)
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#ifdef VM_X86_64
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/*
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* intrinsic functions only supported by x86-64 windows as of 2k3sp1
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*/
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unsigned __int64 __rdtsc(void);
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void __stosw(unsigned short *, unsigned short, size_t);
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void __stosd(unsigned long *, unsigned long, size_t);
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void _mm_pause(void);
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#pragma intrinsic(__rdtsc, __stosw, __stosd, _mm_pause)
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unsigned char _BitScanForward64(unsigned long *, unsigned __int64);
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unsigned char _BitScanReverse64(unsigned long *, unsigned __int64);
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#pragma intrinsic(_BitScanForward64, _BitScanReverse64)
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#endif /* VM_X86_64 */
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unsigned char _BitScanForward(unsigned long *, unsigned long);
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unsigned char _BitScanReverse(unsigned long *, unsigned long);
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#pragma intrinsic(_BitScanForward, _BitScanReverse)
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unsigned char _bittest(const long *, long);
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unsigned char _bittestandset(long *, long);
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unsigned char _bittestandreset(long *, long);
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unsigned char _bittestandcomplement(long *, long);
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#pragma intrinsic(_bittest, _bittestandset, _bittestandreset, _bittestandcomplement)
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#ifdef VM_X86_64
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unsigned char _bittestandset64(__int64 *, __int64);
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unsigned char _bittestandreset64(__int64 *, __int64);
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#pragma intrinsic(_bittestandset64, _bittestandreset64)
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#endif // VM_X86_64
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#ifdef __cplusplus
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}
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#endif
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#endif // _MSC_VER
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#ifdef __GNUC__
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/*
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* Checked against the Intel manual and GCC --hpreg
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*
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* volatile because reading from port can modify the state of the underlying
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* hardware.
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*
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* Note: The undocumented %z construct doesn't work (internal compiler error)
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* with gcc-2.95.1
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*/
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#define __GCC_IN(s, type, name) \
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static INLINE type \
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name(uint16 port) \
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{ \
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type val; \
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\
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__asm__ __volatile__( \
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"in" #s " %w1, %0" \
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: "=a" (val) \
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: "Nd" (port) \
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); \
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\
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return val; \
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}
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__GCC_IN(b, uint8, INB)
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__GCC_IN(w, uint16, INW)
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__GCC_IN(l, uint32, IN32)
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/*
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* Checked against the Intel manual and GCC --hpreg
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*
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* Note: The undocumented %z construct doesn't work (internal compiler error)
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* with gcc-2.95.1
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*/
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#define __GCC_OUT(s, s2, port, val) do { \
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__asm__( \
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"out" #s " %" #s2 "1, %w0" \
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: \
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: "Nd" (port), "a" (val) \
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); \
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} while (0)
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#define OUTB(port, val) __GCC_OUT(b, b, port, val)
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#define OUTW(port, val) __GCC_OUT(w, w, port, val)
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#define OUT32(port, val) __GCC_OUT(l, , port, val)
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#define GET_CURRENT_EIP(_eip) \
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__asm__ __volatile("call 0\n\tpopl %0" : "=r" (_eip): );
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static INLINE unsigned int
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GetCallerEFlags(void)
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{
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unsigned long flags;
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asm volatile("pushf; pop %0" : "=r"(flags));
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return flags;
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}
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#elif defined(_MSC_VER)
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static INLINE uint8
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INB(uint16 port)
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{
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return (uint8)_inp(port);
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}
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static INLINE void
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OUTB(uint16 port, uint8 value)
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{
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_outp(port, value);
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}
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static INLINE uint16
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INW(uint16 port)
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{
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return _inpw(port);
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}
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static INLINE void
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OUTW(uint16 port, uint16 value)
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{
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_outpw(port, value);
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}
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static INLINE uint32
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IN32(uint16 port)
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{
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return _inpd(port);
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}
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static INLINE void
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OUT32(uint16 port, uint32 value)
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{
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_outpd(port, value);
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}
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#ifndef VM_X86_64
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#ifdef NEAR
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#undef NEAR
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#endif
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#define GET_CURRENT_EIP(_eip) do { \
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__asm call NEAR PTR $+5 \
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__asm pop eax \
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__asm mov _eip, eax \
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} while (0)
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#endif // VM_X86_64
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static INLINE unsigned int
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GetCallerEFlags(void)
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{
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return __getcallerseflags();
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}
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#endif // __GNUC__
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/* Sequence recommended by Intel for the Pentium 4. */
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#define INTEL_MICROCODE_VERSION() ( \
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__SET_MSR(MSR_BIOS_SIGN_ID, 0), \
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__GET_EAX_FROM_CPUID(1), \
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__GET_MSR(MSR_BIOS_SIGN_ID))
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/*
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*-----------------------------------------------------------------------------
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*
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* RDTSC_BARRIER --
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*
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* Implements an RDTSC fence. Instructions executed prior to the
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* fence will have completed before the fence and all stores to
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* memory are flushed from the store buffer.
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*
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* On AMD, MFENCE is sufficient. On Intel, only LFENCE is
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* documented to fence RDTSC, but LFENCE won't drain the store
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* buffer. So, use MFENCE;LFENCE, which will work on both AMD and
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* Intel.
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*
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* It is the callers' responsibility to check for SSE2 before
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* calling this function.
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*
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* Results:
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* None.
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*
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* Side effects:
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* Cause loads and stores prior to this to be globally visible, and
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* RDTSC will not pass.
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*
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*-----------------------------------------------------------------------------
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*/
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static INLINE void
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RDTSC_BARRIER(void)
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{
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#ifdef __GNUC__
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__asm__ __volatile__(
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"mfence \n\t"
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"lfence \n\t"
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::: "memory"
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);
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#elif defined _MSC_VER
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/* Prevent compiler from moving code across mfence/lfence. */
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_ReadWriteBarrier();
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_mm_mfence();
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_mm_lfence();
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_ReadWriteBarrier();
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#else
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#error No compiler defined for RDTSC_BARRIER
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#endif
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}
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/*
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* Memory Barriers
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* ===============
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*
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* Terminology
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* -----------
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*
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* A compiler memory barrier prevents the compiler from re-ordering memory
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* accesses accross the barrier. It is not a CPU instruction, it is a compiler
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* directive (i.e. it does not emit any code).
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*
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* A CPU memory barrier prevents the CPU from re-ordering memory accesses
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* accross the barrier. It is a CPU instruction.
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*
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* A memory barrier is the union of a compiler memory barrier and a CPU memory
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* barrier. A compiler memory barrier is a useless construct by itself. It is
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* only useful when combined with a CPU memory barrier, to implement a memory
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* barrier.
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*
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* Semantics
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* ---------
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*
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* At the time COMPILER_*_BARRIER were created (and references to them were
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* added to the code), the code was only targetting x86. The intent of the code
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* was really to use a memory barrier, but because x86 uses a strongly ordered
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* memory model, the CPU would not re-order memory accesses, and the code could
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* get away with using just a compiler memory barrier. So COMPILER_*_BARRIER
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* were born and were implemented as compiler memory barriers _on x86_. But
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* make no mistake, _the semantics that the code expects from
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* COMPILER_*_BARRIER are that of a memory barrier_!
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*
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* DO NOT USE!
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* -----------
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*
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* On at least one non-x86 architecture, COMPILER_*_BARRIER are
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* 1) Misnomers
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* 2) Not fine-grained enough to provide the best performance.
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* For the above two reasons, usage of COMPILER_*_BARRIER is now deprecated.
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* _Do not add new references to COMPILER_*_BARRIER._ Instead, precisely
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* document the intent of your code by using
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* <mem_type/purpose>_<before_access_type>_BARRIER_<after_access_type>.
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* Existing references to COMPILER_*_BARRIER are being slowly but surely
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* converted, and when no references are left, COMPILER_*_BARRIER will be
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* retired.
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*
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* Thanks for pasting this whole comment into every architecture header.
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*/
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#if defined __GNUC__
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# define COMPILER_READ_BARRIER() COMPILER_MEM_BARRIER()
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# define COMPILER_WRITE_BARRIER() COMPILER_MEM_BARRIER()
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# define COMPILER_MEM_BARRIER() __asm__ __volatile__("" ::: "memory")
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#elif defined _MSC_VER
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# define COMPILER_READ_BARRIER() _ReadBarrier()
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# define COMPILER_WRITE_BARRIER() _WriteBarrier()
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# define COMPILER_MEM_BARRIER() _ReadWriteBarrier()
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#endif
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/*
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* Memory barriers. These take the form of
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*
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* <mem_type/purpose>_<before_access_type>_BARRIER_<after_access_type>
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*
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* where:
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* <mem_type/purpose> is either SMP, DMA, or MMIO.
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* <*_access type> is either R(load), W(store) or RW(any).
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*
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* Above every use of these memory barriers in the code, there _must_ be a
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* comment to justify the use, i.e. a comment which:
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*
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* 1) Precisely identifies which memory accesses must not be re-ordered across
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* the memory barrier.
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* 2) Explains why it is important that the memory accesses not be re-ordered.
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*
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* Thanks for pasting this whole comment into every architecture header.
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*
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* On x86, we only need to care specifically about store-load reordering on
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* normal memory types. In other cases, only a compiler barrier is needed. The
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* ST_LD barrier is implemented with a locked xor operation (instead of the
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* mfence instruction) for performance reasons. See PR 1674199 for more
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* details.
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*
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* On x64, special instructions are only provided for load-load (lfence) and
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* store-store (sfence) ordering, and they don't apply to normal memory.
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*/
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static INLINE void
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SMP_W_BARRIER_R(void)
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{
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volatile long temp;
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COMPILER_MEM_BARRIER();
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#if defined __GNUC__
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__asm__ __volatile__ (
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"lock xorl $1, %0\n"
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: "+m" (temp)
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: /* no additional inputs */
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: "cc");
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#elif defined _MSC_VER
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_InterlockedXor(&temp, 1);
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#else
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#error SMP_W_BARRIER_R not defined for this compiler
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#endif
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COMPILER_MEM_BARRIER();
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}
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#define SMP_R_BARRIER_R() COMPILER_READ_BARRIER()
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#define SMP_R_BARRIER_W() COMPILER_MEM_BARRIER()
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#define SMP_R_BARRIER_RW() COMPILER_MEM_BARRIER()
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#define SMP_W_BARRIER_W() COMPILER_WRITE_BARRIER()
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#define SMP_W_BARRIER_RW() SMP_W_BARRIER_R()
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#define SMP_RW_BARRIER_R() SMP_W_BARRIER_R()
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#define SMP_RW_BARRIER_W() COMPILER_MEM_BARRIER()
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#define SMP_RW_BARRIER_RW() SMP_W_BARRIER_R()
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/*
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* Like the above, only for use with observers other than CPUs,
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* i.e. DMA masters.
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*/
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#define DMA_R_BARRIER_R() SMP_R_BARRIER_R()
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#define DMA_R_BARRIER_W() SMP_R_BARRIER_W()
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#define DMA_R_BARRIER_RW() SMP_R_BARRIER_RW()
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#define DMA_W_BARRIER_R() SMP_W_BARRIER_R()
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#define DMA_W_BARRIER_W() SMP_W_BARRIER_W()
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#define DMA_W_BARRIER_RW() SMP_W_BARRIER_RW()
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#define DMA_RW_BARRIER_R() SMP_RW_BARRIER_R()
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#define DMA_RW_BARRIER_W() SMP_RW_BARRIER_W()
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#define DMA_RW_BARRIER_RW() SMP_RW_BARRIER_RW()
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/*
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* And finally a set for use with MMIO accesses.
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*/
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#define MMIO_R_BARRIER_R() SMP_R_BARRIER_R()
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#define MMIO_R_BARRIER_W() SMP_R_BARRIER_W()
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#define MMIO_R_BARRIER_RW() SMP_R_BARRIER_RW()
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#define MMIO_W_BARRIER_R() SMP_W_BARRIER_R()
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#define MMIO_W_BARRIER_W() SMP_W_BARRIER_W()
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#define MMIO_W_BARRIER_RW() SMP_W_BARRIER_RW()
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#define MMIO_RW_BARRIER_R() SMP_RW_BARRIER_R()
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#define MMIO_RW_BARRIER_W() SMP_RW_BARRIER_W()
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#define MMIO_RW_BARRIER_RW() SMP_RW_BARRIER_RW()
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#endif // _VM_BASIC_ASM_X86_COMMON_H_
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