Mikio Hara
695db2964e
Remove monolithic OpenFlow switch. Add userspace datapath. Fix BUG#13: Revise check wildcards for in_port != out_port output validation. Fix BUG#30: Made use of get_jiffies_64 instead of jiffies. Fix BUG#31: Fix NetFPGA crash in case of test_delete test harness run. Fix BUG#32: Add stack depth limitation to avoid inifinite loop in log_backtrace. Fix BUG#33: Improve NetFPGA kernel extension and NetFPGA image to support MAC address rewrite features (two actions) on NetFPGA enabled OpenFlow switch. Fix BUG#34: Add NetFPGA kernel extension source codes to create distribution package with NetFPGA correctly. Fix BUG#38: Improve regression test for FLOW_MOD ACTION SET_DL_SRC and SET_DL_DST. Fix BUG#39: Correct misunderstanding of byte order ops for OFPAT_XXX.
425 lines
15 KiB
C
425 lines
15 KiB
C
/* ****************************************************************************
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* $Id: nf2.h 3546 2008-04-03 00:12:27Z grg $
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*
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* Module: nf2.h
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* Project: NetFPGA 2 Linux Kernel Driver
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* Description: Header file for kernel driver
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*
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* Change history:
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*
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*/
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#ifndef _NF2_H
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#define _NF2_H 1
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#define NF2_DEV_NAME "nf2"
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#include <linux/sockios.h>
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/* Maximum number of interfaces */
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#ifndef MAX_IFACE
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#define MAX_IFACE 4
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#endif
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/*
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* Register names and locations.
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*
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* Note that these names are not necessarily identical to
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* those in NF2/hw/common/src/defines
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*/
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/* CPCI registers */
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#define CPCI_REG_ID 0x000
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#define CPCI_REG_BOARD_ID 0x004
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#define CPCI_REG_CTRL 0x008
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#define CPCI_REG_RESET 0x00c
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#define CPCI_REG_ERROR 0x010
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#define CPCI_REG_DUMMY 0x020
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#define CPCI_REG_INTERRUPT_MASK 0x040
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#define CPCI_REG_INTERRUPT_STATUS 0x044
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#define CPCI_REG_PROG_DATA 0x100
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#define CPCI_REG_PROG_STATUS 0x104
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#define CPCI_REG_PROG_CTRL 0x108
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#define CPCI_REG_DMA_I_ADDR 0x140
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#define CPCI_REG_DMA_E_ADDR 0x144
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#define CPCI_REG_DMA_I_SIZE 0x148
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#define CPCI_REG_DMA_E_SIZE 0x14c
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#define CPCI_REG_DMA_I_CTRL 0x150
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#define CPCI_REG_DMA_E_CTRL 0x154
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#define CPCI_REG_DMA_MAX_XFER_TIME 0x180
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#define CPCI_REG_DMA_MAX_RETRIES 0x184
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#define CPCI_REG_CNET_MAX_XFER_TIME 0x188
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#define CPCI_REG_DMA_I_PKT_CNT 0x400
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#define CPCI_REG_DMA_E_PKT_CNT 0x404
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#define CPCI_REG_CPCI_REG_RD_CNT 0x408
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#define CPCI_REG_CPCI_REG_WR_CNT 0x40c
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#define CPCI_REG_CNET_REG_RD_CNT 0x410
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#define CPCI_REG_CNET_REG_WR_CNT 0x414
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#define CPCI_REG_N_CLK_COUNT 0x500
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#define CPCI_REG_P_MAX 0x504
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#define CPCI_REG_N_EXP 0x508
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#define CPCI_REG_P_CLK_CTR 0x510
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#define CPCI_REG_RESET_CTR 0x520
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/* Base address for CNET registers */
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#define CNET_REG_BASE 0x400000
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/* Added by nweaver for building memory manipulation
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utilities */
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/* 2 MB SRAM size on current board, MAX and SIZE will
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need to be changed if upgraded to 4 MB SRAMs */
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#define SRAM_SIZE 0x200000
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#define SRAM_1_BASE 0x800000
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#define SRAM_1_MAX 0x9FFFFF
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#define SRAM_2_BASE 0xC00000
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#define SRAM_2_MAX 0xDFFFFF
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/* end nweaver addition */
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/* Device ID registers */
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#define NF2_DEVICE_ID 0x0400000
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#define NF2_REVISION 0x0400004
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#define NF2_DEVICE_STR 0x0400008
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/* CNET registers */
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#define CNET_REG_ID (CNET_REG_BASE + 0x000)
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#define CNET_REG_CTRL (CNET_REG_BASE + 0x004)
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#define CNET_REG_RESET (CNET_REG_BASE + 0x008)
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#define CNET_REG_ERROR (CNET_REG_BASE + 0x00C)
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#define CNET_REG_ENABLE (CNET_REG_BASE + 0x010)
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#define CNET_REG_WR_SRAM1_EOP (CNET_REG_BASE + 0x0F0)
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#define CNET_REG_RD_SRAM1_EOP (CNET_REG_BASE + 0x0F4)
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#define CNET_REG_WR_SRAM2_EOP (CNET_REG_BASE + 0x0F8)
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#define CNET_REG_RD_SRAM2_EOP (CNET_REG_BASE + 0x0FC)
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#define CNET_REG_MF_STATUS_0 (CNET_REG_BASE + 0x100)
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#define CNET_REG_MF_TX_PKTS_SENT_0 (CNET_REG_BASE + 0x104)
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#define CNET_REG_MF_RX_PKTS_RCVD_0 (CNET_REG_BASE + 0x108)
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#define CNET_REG_MF_RX_PKTS_LOST_0 (CNET_REG_BASE + 0x10C)
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#define CNET_REG_MAC_CONFIG_0 (CNET_REG_BASE + 0x110)
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#define CNET_REG_MF_STATUS_1 (CNET_REG_BASE + 0x140)
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#define CNET_REG_MF_TX_PKTS_SENT_1 (CNET_REG_BASE + 0x144)
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#define CNET_REG_MF_RX_PKTS_RCVD_1 (CNET_REG_BASE + 0x148)
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#define CNET_REG_MF_RX_PKTS_LOST_1 (CNET_REG_BASE + 0x14C)
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#define CNET_REG_MAC_CONFIG_1 (CNET_REG_BASE + 0x150)
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#define CNET_REG_MF_STATUS_2 (CNET_REG_BASE + 0x180)
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#define CNET_REG_MF_TX_PKTS_SENT_2 (CNET_REG_BASE + 0x184)
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#define CNET_REG_MF_RX_PKTS_RCVD_2 (CNET_REG_BASE + 0x188)
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#define CNET_REG_MF_RX_PKTS_LOST_2 (CNET_REG_BASE + 0x18C)
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#define CNET_REG_MAC_CONFIG_2 (CNET_REG_BASE + 0x190)
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#define CNET_REG_MF_STATUS_3 (CNET_REG_BASE + 0x1C0)
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#define CNET_REG_MF_TX_PKTS_SENT_3 (CNET_REG_BASE + 0x1C4)
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#define CNET_REG_MF_RX_PKTS_RCVD_3 (CNET_REG_BASE + 0x1C8)
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#define CNET_REG_MF_RX_PKTS_LOST_3 (CNET_REG_BASE + 0x1CC)
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#define CNET_REG_MAC_CONFIG_3 (CNET_REG_BASE + 0x1D0)
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#define CNET_REG_RXQ_NUM_PKTS_0 (CNET_REG_BASE + 0x200)
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#define CNET_REG_RXQ_POINTERS_0 (CNET_REG_BASE + 0x204)
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#define CNET_REG_RXQ_NUM_PKTS_1 (CNET_REG_BASE + 0x240)
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#define CNET_REG_RXQ_POINTERS_1 (CNET_REG_BASE + 0x244)
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#define CNET_REG_RXQ_NUM_PKTS_2 (CNET_REG_BASE + 0x280)
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#define CNET_REG_RXQ_POINTERS_2 (CNET_REG_BASE + 0x284)
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#define CNET_REG_RXQ_NUM_PKTS_3 (CNET_REG_BASE + 0x2C0)
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#define CNET_REG_RXQ_POINTERS_3 (CNET_REG_BASE + 0x2C4)
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#define CNET_REG_MF_RX_PKTS_LOST_BAD_FCS_0 (CNET_REG_BASE + 0x114)
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#define CNET_REG_MF_RX_PKTS_LOST_FULL_FIFO_0 (CNET_REG_BASE+0x118)
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#define CNET_REG_MF_RX_GOOD_PKTS_RCVD_0 (CNET_REG_BASE+0x11C)
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#define CNET_REG_MF_RX_GOOD_BYTES_RCVD_0 (CNET_REG_BASE+0x120)
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#define CNET_REG_MF_TX_BYTES_SENT_0 (CNET_REG_BASE+0x124)
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#define CNET_REG_MF_RX_PKTS_LOST_BAD_FCS_1 (CNET_REG_BASE+0x154)
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#define CNET_REG_MF_RX_PKTS_LOST_FULL_FIFO_1 (CNET_REG_BASE+0x158)
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#define CNET_REG_MF_RX_GOOD_PKTS_RCVD_1 (CNET_REG_BASE+0x15C)
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#define CNET_REG_MF_RX_GOOD_BYTES_RCVD_1 (CNET_REG_BASE+0x160)
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#define CNET_REG_MF_TX_BYTES_SENT_1 (CNET_REG_BASE+0x164)
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#define CNET_REG_MF_RX_PKTS_LOST_BAD_FCS_2 (CNET_REG_BASE+0x194)
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#define CNET_REG_MF_RX_PKTS_LOST_FULL_FIFO_2 (CNET_REG_BASE+0x198)
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#define CNET_REG_MF_RX_GOOD_PKTS_RCVD_2 (CNET_REG_BASE+0x19C)
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#define CNET_REG_MF_RX_GOOD_BYTES_RCVD_2 (CNET_REG_BASE+0x1A0)
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#define CNET_REG_MF_TX_BYTES_SENT_2 (CNET_REG_BASE+0x1A4)
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#define CNET_REG_MF_RX_PKTS_LOST_BAD_FCS_3 (CNET_REG_BASE+0x1D4)
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#define CNET_REG_MF_RX_PKTS_LOST_FULL_FIFO_3 (CNET_REG_BASE+0x1D8)
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#define CNET_REG_MF_RX_GOOD_PKTS_RCVD_3 (CNET_REG_BASE+0x1DC)
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#define CNET_REG_MF_RX_GOOD_BYTES_RCVD_3 (CNET_REG_BASE+0x1E0)
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#define CNET_REG_MF_TX_BYTES_SENT_3 (CNET_REG_BASE+0x1E4)
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#define CNET_MAC_CLK_CHK_CTRL (CNET_REG_BASE + 0xF00)
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#define CNET_MAC_CLK_CHK_CNT_VALUE (CNET_REG_BASE + 0xF04)
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/* Base address for CNET PHY registers */
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#define PHY_REG_BASE 0x600000
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#define PHY_REG_CMD (PHY_REG_BASE)
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#define PHY_REG_STATUS (PHY_REG_BASE)
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/*
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* CPCI register masks
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*/
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/* ID Masks */
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#define ID_VERSION 0x00FFFFFF
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#define ID_REVISION 0xFF000000
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/* Board ID Masks */
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#define BOARD_ID 0x00000F00
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#define BOARD_ID_CONTROL 0x00000001
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/* Control masks */
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#define CTRL_CNET_RESET 0x00000100
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#define CTRL_LED 0x00000001
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/* RESET masks */
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#define RESET_CPCI 0x00000001
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/* Error masks */
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#define ERR_CNET_READ_TIMEOUT 0x02000000
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#define ERR_CNET_ERROR 0x01000000
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#define ERR_PROG_BUF_OVERFLOW 0x00020000
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#define ERR_PROG_ERROR 0x00010000
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#define ERR_DMA_TIMEOUT 0x00000400
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#define ERR_DMA_RETRY_CNT_EXPIRED 0x00000200
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#define ERR_DMA_BUF_OVERFLOW 0x00000100
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#define ERR_DMA_RD_SIZE_ERROR 0x00000040
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#define ERR_DMA_WR_SIZE_ERROR 0x00000020
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#define ERR_DMA_RD_ADDR_ERROR 0x00000010
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#define ERR_DMA_WR_ADDR_ERROR 0x00000008
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#define ERR_DMA_RD_MAC_ERROR 0x00000004
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#define ERR_DMA_WR_MAC_ERROR 0x00000002
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#define ERR_DMA_FATAL_ERROR 0x00000001
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#define ERR_DMA_SETUP_ERROR ( ERR_DMA_WR_MAC_ERROR | \
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ERR_DMA_RD_MAC_ERROR | \
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ERR_DMA_WR_ADDR_ERROR | \
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ERR_DMA_RD_ADDR_ERROR | \
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ERR_DMA_WR_SIZE_ERROR | \
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ERR_DMA_RD_SIZE_ERROR )
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/* Interrupt masks */
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#define INT_DMA_RX_COMPLETE 0x80000000
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#define INT_DMA_TX_COMPLETE 0x40000000
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#define INT_PHY_INTERRUPT 0x20000000
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#define INT_PKT_AVAIL 0x00000100
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#define INT_CNET_ERROR 0x00000020
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#define INT_CNET_READ_TIMEOUT 0x00000010
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#define INT_PROG_ERROR 0x00000008
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#define INT_DMA_TRANSFER_ERROR 0x00000004
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#define INT_DMA_SETUP_ERROR 0x00000002
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#define INT_DMA_FATAL_ERROR 0x00000001
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#define INT_UNKNOWN ~(INT_DMA_RX_COMPLETE | \
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INT_DMA_TX_COMPLETE | \
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INT_PHY_INTERRUPT | \
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INT_PKT_AVAIL | \
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INT_CNET_ERROR | \
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INT_CNET_READ_TIMEOUT | \
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INT_PROG_ERROR | \
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INT_DMA_TRANSFER_ERROR | \
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INT_DMA_SETUP_ERROR | \
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INT_DMA_FATAL_ERROR)
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/* Programming status */
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#define PROG_INIT 0x00010000
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#define PROG_DONE 0x00000100
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#define PROG_FIFO_EMPTY 0x00000002
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#define PROG_IN_PROGRESS 0x00000001
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/* Programming control */
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#define PROG_CTRL_RESET 0x00000001
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/* DMA control */
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#define DMA_CTRL_MAC 0x00000300
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#define DMA_CTRL_OWNER 0x00000001
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/*
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* CNET register masks
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*/
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/* Reset masks */
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#define CNET_RESET_MAC 0x0000000F
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#define CNET_RESET_MAC_3 0x00000008
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#define CNET_RESET_MAC_2 0x00000004
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#define CNET_RESET_MAC_1 0x00000002
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#define CNET_RESET_MAC_0 0x00000001
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/* Error masks */
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#define CNET_ERROR_TX_UNDERRUN_MAC 0x000000F0
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#define CNET_ERROR_TX_UNDERRUN_MAC_3 0x00000080
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#define CNET_ERROR_TX_UNDERRUN_MAC_2 0x00000040
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#define CNET_ERROR_TX_UNDERRUN_MAC_1 0x00000020
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#define CNET_ERROR_TX_UNDERRUN_MAC_0 0x00000010
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#define CNET_ERROR_TX_OVERRUN_MAC 0x0000000F
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#define CNET_ERROR_TX_OVERRUN_MAC_3 0x00000008
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#define CNET_ERROR_TX_OVERRUN_MAC_2 0x00000004
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#define CNET_ERROR_TX_OVERRUN_MAC_1 0x00000002
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#define CNET_ERROR_TX_OVERRUN_MAC_0 0x00000001
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/* Enable masks */
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#define CNET_ENABLE_RX_FIFO 0x0000F000
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#define CNET_ENABLE_RX_FIFO_3 0x00008000
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#define CNET_ENABLE_RX_FIFO_2 0x00004000
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#define CNET_ENABLE_RX_FIFO_1 0x00002000
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#define CNET_ENABLE_RX_FIFO_0 0x00001000
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#define CNET_ENABLE_TX_MAC 0x00000F00
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#define CNET_ENABLE_TX_MAC_3 0x00000800
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#define CNET_ENABLE_TX_MAC_2 0x00000400
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#define CNET_ENABLE_TX_MAC_1 0x00000200
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#define CNET_ENABLE_TX_MAC_0 0x00000100
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#define CNET_ENABLE_DEBUG_TRISTATE 0x00000004
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#define CNET_ENABLE_INGRESS_ARBITER 0x00000002
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#define CNET_ENABLE_RX_DMA 0x00000001
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/* MF Status masks */
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#define CNET_MF_STATUS_RX_FIFO_EMPTY 0x02000000
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#define CNET_MF_STATUS_RX_PKT_AVAIL 0x01000000
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#define CNET_MF_STATUS_RX_NUM_PKTS 0x00FF0000
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#define CNET_MF_STATUS_TX_FIFO_FULL 0x00000200
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#define CNET_MF_STATUS_TX_FIFO_NO_MAX_PKT 0x00000100
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#define CNET_MF_STATUS_TX_NUM_PKTS 0x000000FF
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/* MAC Config masks */
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#define CNET_MAC_CFG_FULL_DUPLEX 0x00000020
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#define CNET_MAC_CFG_TX_FCS_SUPPLIED 0x00000010
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#define CNET_MAC_CFG_RX_WANT_FCS 0x00000008
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#define CNET_MAC_CFG_JUMBO_ENABLE 0x00000004
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#define CNET_MAC_CFG_SPEED 0x00000002
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#define CNET_MAC_CFG_1000_MBPS 0x00000002
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#define CNET_MAC_CFG_100_MBPS 0x00000001
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#define CNET_MAC_CFG_10_MBPS 0x00000000
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#define CNET_RXQ_WR_PTR 0x00FF0000
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#define CNET_RXQ_RD_PTR 0x000000FF
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/* Phy register masks */
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#define PHY_RD_WR 0x80000000
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#define PHY_PHY 0x03000000
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#define PHY_ADDR 0x001F0000
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#define PHY_DATA 0x0000FFFF
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#define PHY_DONE 0x80000000
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#define PHY_DONE_CNT 0x001F0000
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/* Defines to calculate register values */
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/* CPCI Funcs */
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#define NF2_GET_VERSION(x) (x & 0xFFFFFF)
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#define NF2_GET_REVISION(x) ((x & 0xFF000000) >> 24)
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#define NF2_GET_BOARD_ID(x) ((x & BOARD_ID) >> 8)
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#define NF2_GET_CONTROL(x) (x & BOARD_ID_CONTROL)
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#define NF2_GET_CNET_RESET(x) ((x & CTRL_CNET_RESET) >> 8)
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#define NF2_GET_LED(x) (x & CTRL_LED)
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#define NF2_GET_RESET(x) (x & RESET_CPCI)
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#define NF2_GET_CNET_READ_TIMEOUT(x) ((x & ERR_CNET_READ_TIMEOUT) >> 25)
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#define NF2_GET_CNET_ERROR(x) ((x & ERR_CNET_ERROR) >> 24)
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#define NF2_GET_PROG_BUF_OVERFLOW(x) ((x & ERR_PROG_BUF_OVERFLOW) >> 12)
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#define NF2_GET_PROG_ERROR(x) ((x & ERR_PROG_ERROR) >> 11)
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#define NF2_GET_DMA_TIMEOUT(x) ((x & ERR_DMA_TIMEOUT) >> 10)
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#define NF2_GET_DMA_RETRY_CNT_EXPIRED(x) \
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((x & ERR_DMA_RETRY_CNT_EXPIRED) >> 9)
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#define NF2_GET_DMA_BUF_OVERFLOW(x) ((x & ERR_DMA_BUF_OVERFLOW) >> 8)
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#define NF2_GET_DMA_RD_SIZE_ERROR(x) ((x & ERR_DMA_RD_SIZE_ERROR) >> 6)
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#define NF2_GET_DMA_WR_SIZE_ERROR(x) ((x & ERR_DMA_WR_SIZE_ERROR) >> 5)
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#define NF2_GET_DMA_RD_ADDR_ERROR(x) ((x & ERR_DMA_RD_ADDR_ERROR) >> 4)
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#define NF2_GET_DMA_WR_ADDR_ERROR(x) ((x & ERR_DMA_WR_ADDR_ERROR) >> 3)
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#define NF2_GET_DMA_RD_MAC_ERROR(x) ((x & ERR_DMA_RD_MAC_ERROR) >> 2)
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#define NF2_GET_DMA_WR_MAC_ERROR(x) ((x & ERR_DMA_WR_MAC_ERROR) >> 1)
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#define NF2_GET_DMA_FATAL_ERROR(x) (x & ERR_DMA_FATAL_ERROR)
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#define NF2_GET_INT_DMA_TX_COMPLETE(x) ((x & INT_DMA_TX_COMPLETE) >> 31)
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#define NF2_GET_INT_DMA_RX_COMPLETE(x) ((x & INT_DMA_RX_COMPLETE) >> 30)
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#define NF2_GET_INT_PHY_INTERRUPT(x) ((x & INT_PHY_INTERRUPT) >> 29)
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#define NF2_GET_INT_PKT_AVAIL(x) ((x & INT_PKT_AVAIL) >> 8)
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#define NF2_GET_INT_CNET_ERROR(x) ((x & INT_CNET_ERROR) >> 5)
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#define NF2_GET_INT_CNET_READ_TIMEOUT(x) \
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((x & INT_CNET_READ_TIMEOUT) >> 4)
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#define NF2_GET_INT_PROG_ERROR(x) ((x & INT_PROG_ERROR) >> 3)
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#define NF2_GET_INT_DMA_TRANSFER_ERROR(x) \
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((x & INT_DMA_TRANSFER_ERROR) >> 2)
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#define NF2_GET_INT_DMA_SETUP_ERROR(x) ((x & INT_DMA_SETUP_ERROR) >> 1)
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#define NF2_GET_INT_DMA_FATAL_ERROR(x) (x & INT_DMA_FATAL_ERROR)
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#define NF2_GET_PROG_INIT(x) ((x & PROG_INIT) >> 16)
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#define NF2_GET_PROG_DONE(x) ((x & PROG_DONE) >> 8)
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#define NF2_GET_PROG_FIFO_EMPTY(x) ((x & PROG_FIFO_EMPTY) >> 1)
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#define NF2_GET_PROG_IN_PROGRESS(x) (x & PROG_IN_PROGRESS)
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#define NF2_GET_DMA_CTRL_MAC(x) ((x & DMA_CTRL_MAC) >> 8)
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#define NF2_GET_DMA_CTRL_OWNER(x) (x & DMA_CTRL_OWNER)
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#define NF2_SET_DMA_CTRL_MAC(x) (x << 8)
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/* CNET Funcs */
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#define NF2_GET_CNET_VERSION(x) ((x & 0xFFFF0000) >> 16)
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#define NF2_GET_CNET_DEVICE_ID(x) (x & 0xFFFF)
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#define NF2_GET_CNET_RESET_MAC(x) (x & CNET_RESET_MAC)
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#define NF2_GET_CNET_ERROR_TX_UNDERRUN_MAC(x) \
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((x & CNET_ERROR_TX_UNDERRUN_MAC) >> 4)
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#define NF2_GET_CNET_ERROR_TX_OVERRUN_MAC(x) \
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(x & CNET_ERROR_TX_OVERRUN_MAC)
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#define NF2_GET_CNET_ENABLE_RX_FIFO(x) ((x & CNET_ENABLE_RX_FIFO) >> 12)
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#define NF2_GET_CNET_ENABLE_TX_MAC(x) ((x & CNET_ENABLE_TX_MAC) >> 8)
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#define NF2_GET_CNET_ENABLE_DEBUG_TRISTATE(x) \
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((x & CNET_ENABLE_DEBUG_TRISTATE) >> 2)
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#define NF2_GET_CNET_ENABLE_INGRESS_ARBITER(x) \
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((x & CNET_ENABLE_INGRESS_ARBITER) >> 1)
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#define NF2_GET_CNET_ENABLE_RX_DMA(x) (x & CNET_ENABLE_RX_DMA)
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#define NF2_GET_CNET_MF_STATUS_RX_FIFO_EMPTY(x) \
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((x & CNET_MF_STATUS_RX_FIFO_EMPTY) >> 25)
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#define NF2_GET_CNET_MF_STATUS_RX_PKT_AVAIL(x) \
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((x & CNET_MF_STATUS_RX_PKT_AVAIL) >> 24)
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#define NF2_GET_CNET_MF_STATUS_RX_NUM_PKTS(x) \
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((x & CNET_MF_STATUS_RX_NUM_PKTS) >> 16)
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#define NF2_GET_CNET_MF_STATUS_TX_FIFO_FULL(x) \
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((x & CNET_MF_STATUS_TX_FIFO_FULL) >> 9)
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#define NF2_GET_CNET_MF_STATUS_TX_FIFO_NO_MAX_PKT(x) \
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((x & CNET_MF_STATUS_TX_FIFO_NO_MAX_PKT) >> 8)
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#define NF2_GET_CNET_MF_STATUS_TX_NUM_PKTS(x) \
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(x & CNET_MF_STATUS_TX_NUM_PKTS)
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#define NF2_GET_CNET_MAC_CFG_FULL_DUPLEX(x) \
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((x & CNET_MAC_CFG_FULL_DUPLEX) >> 5)
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#define NF2_GET_CNET_MAC_CFG_TX_FCS_SUPPLIED(x) \
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((x & CNET_MAC_CFG_TX_FCS_SUPPLIED) >> 4)
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#define NF2_GET_CNET_MAC_CFG_RX_WANT_FCS(x) \
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((x & CNET_MAC_CFG_RX_WANT_FCS) >> 3)
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#define NF2_GET_CNET_MAC_CFG_JUMBO_ENABLE(x) \
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((x & CNET_MAC_CFG_JUMBO_ENABLE) >> 2)
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#define NF2_GET_CNET_MAC_CFG_SPEED(x) \
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(x & CNET_MAC_CFG_SPEED)
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#define NF2_GET_CNET_RXQ_WR_PTR(x) ((x & CNET_RXQ_WR_PTR) >> 16)
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#define NF2_GET_CNET_RXQ_RD_PTR(x) (x & CNET_RXQ_RD_PTR)
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/* PHY functions */
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#define NF2_SET_PHY_IS_READ(x) (x << 31)
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#define NF2_SET_PHY_SELECT(x) (x << 24)
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#define NF2_SET_PHY_ADDR(x) (x << 16)
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#define NF2_SET_PHY_DATA(x) (x)
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#define NF2_GET_PHY_DATA(x) (x & PHY_DATA)
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#define NF2_GET_PHY_DONE(x) ((x & PHY_DONE) >> 31)
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#define NF2_GET_PHY_DONE_CNT(x) ((x & PHY_DONE_CNT) >> 16)
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/*
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* IOCTLs
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*/
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#define SIOCREGREAD SIOCDEVPRIVATE
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#define SIOCREGWRITE (SIOCDEVPRIVATE + 1)
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/*
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* Structure for transferring register data via an IOCTL
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*/
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struct nf2reg {
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unsigned int reg;
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unsigned int val;
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};
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#endif
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